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Welcome to
Today is: Tuesday March 21, 2023

My Mission

To provide customized hands-on support with detailed SPICE analysis in the areas of transistor-level design; critical path simulation; noise analysis; modeling/IBIS; and characterization.

Site Profile was founded in 2005 by Mr. Doran David, MSEE.   Mr. David is an IC Design Engineer having 15+ years experience where critical-path simulations are required.  From 1984 through 2002 Mr. David was was employed at Texas Instruments and Toshiba America Electronic Components,  respectively, after which he embarked on the next phase of his career providing similar such support on a consulting/project basis.   This site is intended to showcase Mr. David's work and supplement his resume.


Work Summary of Doran David

Mr. David began his engineering career in 1984 at Texas Instruments (TI) 74HC CMOS product line as a Product Engineer with responsibility for 30% of TI's CMOS sales. Working as a CMOS and ASIC Product Engineer, he became aware of the intense effort and production costs associated with "re-spinning" an IC design once timing and other such functions do not meet specification.  Mr. David then entered the design arena in 1986 at TI's SPDC (Semiconductor Process and Design Center) where he contributed to TI's first working Military 16K and 64K SRAMs.  His SPICE simulations for SRAM noise reduction techniques were used in preparing a patent. "Noise Reduction for Output Drivers", (awarded Feb. 1989) on the methods used on TI's Military SRAMs, as well as his Masters thesis "Noise Reduction Techniques for CMOS SRAMs".   These methods later proved to yield the desired noise enhancements and were verified on actual silicon (explained in thesis).  His SPICE simulations we mostly full-chip simulations using SPICE multiplication factor to model the loading of all elements in the chip, including parasitics.

In 1989 Mr. David continued his simulation work at TI's Cache Tage products, as well as DSP groups at TI (JPEG & MPEG Projects), where he had responsibility for RAMs, ROMs and custom cells where critical paths simulations were required.

In 1993-94 Mr. David worked one year on-site in San Jose for technology transfer of a MPEG2 video Codec to TI from California vendor so that TI can second-source their video Codec. 

In 1997 Mr. David joined Toshiba's ASIC Design Center in Dallas where he closely worked with key customers on timing & noise simulations; Verilog sign-off flow; and generated IBIS & cell characterization models using his own custom HSPICE test benches.

In 2003 Mr. David began a series of contract positions utilizing his detailed simulations.


In 2009-2011 Mr. David enhanced his hardware skills to include IT by taking courses with programming in C#, Perl scripting,Visual Studio, SQL Server, and received MCTS and CIW associate certifications.  Then applied the CIW to website development work at Abfitproducts (part time in 2010) while searching for engineering work in his core competence.


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