search tips

advanced search

site search by freefind

                        

 

                                        

hspice

Nanosim

spectre

Ultrasim  

smartspice  

Welcome to Spiceguy.net.
Today is: Friday May 24, 2019

IBIS Modeling  

 

1.  Introduction

IBIS stands for Input/Output Buffer Information Specification

 

Purpose of an IBIS model: A way to present the electrical characteristics of an input, output, or I/O buffer behaviorally, i.e., without revealing the underlying transistor or process information.


The Input/Output Buffer Information Specification (IBIS) was developed by the IBIS Open Forum, which is affiliated with the Electronic Industries Alliance (EIA).  The first spec version 1.0 came out in April 1993, and the current version is 5.0 from August 2008.  IBIS specifies a standard form to present information in ASCII format, using special files.  This information describes the behavior of various I/O buffers that send electrical signals outside the silicon chip, or receive such signals.

 

This type of information includes:

  1. Output I-V curves for output buffers, in LOW and HIGH states.

  2. Input I-V curves of the power clamp or ESD diodes.

  3. Rise and fall time of the buffer when switching (dV/dt_r and dV/dt_f).

  4. Values for input or output die capacitance "c_comp".

  5. V(t) curves, describing the exact form of transitions from LOW to HIGH states, and from HIGH to LOW states, for a specified load.

  6. Electrical parameters of the packages.

  7. The characteristics of the package (the values of the lead inductance, resistance, and capacitance)

 

2.  My IBIS Flow using HSPICE and S2IBIS3

My  IBIS Flow document (not shown) consists of the following sections describing how to generate an IBIS model.   The Validation step is a SPICE simulation of the actual circuit together with the IBIS model which demonstrates the integrity of the IBIS model as shown in the last simulation plot below.

  1. Introduction and Pre-modeling information

  2. Procedure to Generate IBIS file Manually using HSPICE Simulations

  3. Specific Instructions for Manual SPICE Simulation to derive IBIS parameters

  4. IBIS model Validation

  5. Procedure to Generate IBIS file Using "S2IBIS3" Java Script, developed at North Carolina State University

  6. Syntax Check of your IBIS model
     

3.  Sample Simulations from IBIS Flow

  1. HSTL 800MHz I/O Simulation Waveform with Output Fixture (Fast / Typical / Slow)

This simulation is for a HSTL 800MHz I/O Buffer's Rising and Falling Waveform used for the IBIS model.   The simulation includes the IBIS spec test fixture R/L/C components at the measurement point.  Curves are shown for Fast/Typical/Slow conditions for before and after the IBIS test fixture.

  (HSTL 800MHz Waveform Simulation for IBIS Model: Click to Enlarge.)           (IBIS Test Fixture: Click to Enlarge.)

   HSTL 800MHz I/O Simulation Waveform with Output Fixture (Fast / Typical / Slow)      IBIS Test Fixture

 

  1. PCI-X  100MHz I/O Simulation Waveform with Output Fixture (Fast / Typical / Slow)

This simulation is for a PCI-X  I/O Buffer's Rising and Falling Waveform used for the IBIS model.   The simulation includes the IBIS spec Test Fixture R/L/C components.

 

  (PCI-X Waveform Simulation for IBIS Model: Click Image to Enlarge)

PCI-X  100MHz I/O Simulation Waveform with Output Fixture (Fast / Typical / Slow)

  

  1. PCI-X **VALIDATION** Simulation Waveform with Output Test Fixture (Typical / Slow / Fast)

This is the IBIS Validation simulation is for a PCI-X I/O Buffer's Rising and Falling Waveforms.   The previous simulation is rerun with the IBIS model instantiated.   The IBIS signal is shown in cyan, and the actual circuit is shown in red.   For this setup we see excellent correlation with only 250pS difference in one transition (Falling edge).   The IBIS model matches the logic voltage levels, as well as the slew rate of the actual circuit.

 

 (PCI-X Validation of IBIS Model vs. Actual Circuit: Click Image to Enlarge)

PCI-X  Validation Simulation Waveform with Output Fixture (Typical / Slow / Fast)

 

4.  Excerpts from Custom HSPICE  Top-Level IBIS Simulations

These are portions HSPICE top level source code used to simulate various IBIS scenarios and generate data for the IBIS model.

 

A)  HSPICE top level deck to measure PCI-X clamp currents for IBIS model

                  (Click Image to Enlarge)

      deck for clamp current

B)  HSPICE top level deck to measure C_comp for IBIS model using AC Analysis

                                (click image to enlarge)

C_comp

C)  HSPICE top level deck to measure IBIS Rising and Falling Waveforms

                    (click image to enlarge)

 Rising / Falling

D) HSPICE top level deck to run IBIS Validation 

This shows how to simulate the IBIS model together with the actual netlist for model validation.

                     (click image to enlarge)

Validation

E) Additional SPICE Code for IBIS Spec Test Fixture used for Rising/Falling Waveforms

  1. IBIS RLC test fixture

  2. IBIS T-Line test fixture (optional)

 

                                            HOME | SPICE | EDUCATION | NEWS     [Back to Top]

Send email to Doran@Spiceguy.net with questions or comments about this web site.  Copyright © 2011 by Spiceguy.net.  Last modified: 12/09/11