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Today is: Tuesday March 21, 2023

Parasitic Extraction & Unix Scripts


1.  Introduction

This section covers a process used to extract SPICE netlist from layout using Cadence tools, and how a UNIX script is used to post-process the SPICE output to generate a formatted table of critical timing arcs for multiple conditions.

The procedure starts by using the Verilog netlist and a DEF (Design Exchange Format) file.   The Verilog contains the path of interest and the DEF has the layout of the circuit.  After some manipulation of the Verilog & DEF,  Cadence QX  can be run to generate the extracted parasitics into a DSPF (Detailed Standard Parasitic Format).  Then using a Mentor tool "V2LVS", we translate the Verilog structural netlist into a LVS SPICE netlist suitable for Calibre, but not HSPICE since the port order will be incorrect for HSPICE.  The port order can be fixed by using a script to generate HSPICE using correct port order from HSPICE cell library.

Then a top-level HSPICE file is created which references the transistor models; process libraries;  the DSPF parasitics file from QX;  and the properly formatted SPICE netlist from V2LVS.   Depending on the size of the netlist, you can choose a platform and simulator to run the simulation.  In this example, the simulation was run on a Linux box using Nanosim at various conditions.


2.  Sample Scripts Showing Steps Described Above


Here is an example showing some key steps described above.   The hyperlinks will pull up sample code as explained below.


  A) Sample Unix script to clean up Verilog or DEF file by  by removing all "\" ,"]" and change all "[" and "/"  to "_".


  B)  Unix script (#!/bin/csh -f)  with sed commands  to replace bad characters in Verilog netlist from Debussy.
Also generates a sorted & uniquified list of all net names from Verilog to extract using Perl script.


      Unix script:  Process_verilog.scr


   Perl script:


  C) Sample script to run QX to generate the DSPF file:


  D) This script generates SPICE netlist from Verilog with proper cell connections and appends the Verilog primitives to the output Verilog file.


  E) Sample script to run V2LVS to generate the SPICE file:


  Summary:  The above scripts will generate the HSPICE netlist and DSPF file with the extracted parasitics from layout.

3.  Setting Up & Running Top-Level HSPICE File for the Extracted Path


Now that we have the HSPICE netlist and extracted parasitics file, we create the top-level HSPICE file which references these, as well as process models and all necessary libraries.   A stimulus library is also needed to exercise all the appropriate inputs to generate the timing waveforms for the desired path.   Measure statements are needed to calculate timing delays.   Probe statements are also needed to output all the desired signals.   This takes some effort depending on your circuit, but I will add a stripped down version for a sample format I use.


A)  HSPICE Top-Level Sample File:


B) Command script to run HSPICE on Linux box:


C) Command script to run Nanosim on Linux box, in case netlist is too big for HSPICE:



Once you succeed in running the simulation, you are ready to process the output.   For this I will show how a UNIX script can extract information from the Spice output and generate a formatted table of the results as follows.



4.  UNIX Script for Post-Processing of Spice (or Nanosim) Output File


The script below will accept either a HSPICE or Nanosim output file for processing.   It extracts data for three conditions in the simulation.   The example shown will have rising & falling clock delays to a clock network and pulsewidth measurements along a clock tree.   All other timing arcs were omitted for simplicity.   Intent here is to show how helpful the Unix script is for extracting the desired results from multiple repetitive simulations into a formatted and readable table.


A) UNIX Script Source


B) UNIX Script Output


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